I/O Signals For Pci Core - Toshiba TX79 Series User Manual

8.6.2 I/O Signals for PCI Core

This section identifies the input and output signals for the PCI core with FIFOs. In Figure
8-13, PCI bus interface signals are shown on the left, and G-Bus interface signals are on the
right. I/O cells are not included in this figure. The core provides data_in, data_out, and
output_enable signals for connecting to the PCI bus pad ring.
PCI Interface Signals
PCI_ADENB
PCI_CBE0_ENB
PCI_CBE1_ENB
PCI_CBE2_ENB
PCI_CBE3_ENB
PCI_CTRL_ENB
PCI_FRAME_ENB
PCI_IRDY_ENB
PCI_PERR_ENB
PCI_PAR_ENB
PCI_REQ_ENB
PCI_RST_INB
PCI_CLK_INB
PCI_GNT_INB
PCI_ADIN
PCI_CBEINB
PCI_FRAME_INB
PCI_IRDY_INB
PCI_TRDY_INB
PCI_DEVSEL_INB
PCI_STOP_INB
PCI_PERR_INB
PCI_PAR_IN
PCI_IDSEL_IN
PCI_REQ_OUTB
PCI_ADOUT
PCI_CBEOUTB
PCI_FRAME_OUTB
PCI_IRDY_OUTB
PCI_TRDY_OUTB
PCI_DEVSEL_OUTB
PCI_STOP_OUTB
PCI_PERR_OUTB
PCI_PAR_OUT
PCI_SERR_OUTB
Figure 8-13 PCI and Application Signals for PCI Core
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 8: PCI/G-Bus Bridge
CORE
32
General
Control
Output
Enables
to I/O
Master
Ports
Control
Master
32
Write
4
FIFO
Control
and Data
from I/O
Ports
Master
Read
FIFO
32 Target
Control
4
Control
and Data
Target
to I/O
Read
Ports
FIFO
Target
Write
FIFO
Configu-
ration
Interface
8-34
To G-Bus
Master
Interface
Control
To G-Bus
Target
Interface
Control
To Configuration
Space
Read/Write
Interface
Control