Table 8-26 Configuration Class; Table 8-27 Configuration Cache - Toshiba TX79 Series User Manual

8.7.6 Class Code Register
Address: 08h
Bits Used: Bits 31:8 are used at this address.
Access: Read Only
The Class Code register contains a code value identifying the generic function of this device.
Bits
23:0 Class Code value
8.7.7 Cache-Line Size Register
Address: 0Ch
Bits Used: Bits 7:0 are used at this address.
Access: Read/Write
For better performance, use values up to 32 (20h). If this register is "00h", then "Memory
Write and Invalidate" commands will be converted into "Memory Write" commands. Also,
"Memory Read Line" and "Memory Read Multiple" commands will be converted into
"Memory Read" commands. Refer to sections 3.1.1, 3.1.2 and 6.2.4 of the PCI Local Bus
Specifications, Ver. 2.15 for further information.
Table 8-27 Configuration Cache-Line Size Register
Bits
7:0 Cache-line size (in terms of 32-bit words)
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 8: PCI/G-Bus Bridge
Table 8-26 Configuration Class Code Register
Description
Description
8-39
Reset
000000h
Reset
00h