C790 Bus Latency; Interrupt Mask Register (Irmsk) - Toshiba TX79 Series User Manual

7.6.16

Interrupt Mask Register (IRMSK)

The Interrupt Mask Register enables/disables interrupt generation.
63
31
Bits Field
63:32 –
31:0 IRMSK
7.6.17 C790 Bus Latency Timer (LT)
The latency timer specifies the maximum period in which the slave has to acknowledge the
master. The counter starts counting down automatically when the master asserts the
SYSASTARTB signal. The counter is decremented at every C790 bus clock cycle. If the
counter is down to zero and the slave device does not respond, a C790 Bus error is
generated and the master generates an interrupt signal to inform the C790 core.
63
31
Bits
63:32
31:0
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 7: C790 Bus/G-Bus Bridge
IRMSK
Table 7-18 C790 Interrupt Mask Register Fields
R/W
Reserved. Must be written as zeroes, and returns
R/O
zeroes when read.
Interrupt Mask
R/W 0: Mask the interrupt request
1: Enable the interrupt request
LT 0
Table 7-19 C790 Bus Latency Timer
Field R/W
Reserved. Must be written as zeroes, and
– R/O
returns zeroes when read.
LT 0 R/W Latency Timer
0
32
32
Description
0
32
32
Description
7-16
32
0
Initial Value
0
0
32
0
Initial Value
0
0xFFFFFFFF