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10.3 Signals
Table 10-2 lists the signals that implement the interface between the Timer/Counter and the
C790. Direct inputs and outputs to the outside of the TX7901 are in the upper case.
Table 10-2 TX7901 Programmable Timer/Counter Signals
Signal Name
gbsBusClk
gbsgData[64:0]
gbsgAddr[31:2]
gcbgTMRRegCSB
gbsgRdB
gbsgWrB
gbsgBStartB
gbsBEB[7:0]
sysResetB
tgdisB
ttest
TIMIN1
TIMIN2
tscanB
tmrgAck32B
tmrgInt0B
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 10: Programmable Timer/Contents
I/O
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Internal Clock from G-Bus, currently 66/50 MHz.
64-bit Data Bus input from the G-Bus to the Timers. Only the lower 24 bits [23:0] are
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used by the timer for writing to its internal registers.
32-bit Address Bus input from the G-Bus to the Timers. Is used internally for correctly
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addressing the device registers inside each timer.
Global Chip Select input signal from the G-Bus to the Timer. The G-Bus generates to
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the timers a single chip select, which is decoded with the help of address information
that is used for selecting each timer. Active Low
Read input signal from the G-Bus to the Timer. This Active Low signal indicates when
a master wants to read from the Timer's internal device registers. This signal remains
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asserted during the entire read cycle.
Write input signal from the G-Bus to the Timer. This Active Low signal indicates when
a master wants to write to the Timer's internal device registers. This signal remains
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asserted during the entire write cycle.
Input Start signal from the G-Bus to the Timer. This Active Low signal indicates that
the G-Bus is starting either a read or a write cycle. This signal is latched internally by
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the timer unit for one cycle, since the gcbgTMRRegCSB signal arrives one clock cycle
later and both signals are needed together to start a read or write cycle on any of the
three timers.
Byte Enable bus inputs from the G-Bus to the Timer. A value of 0xF0 on this bus
indicates that the lower 32 bits [31:0] on the Data Bus are valid and that the upper 32
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bits [63:32] are invalid. The Timer only writes to its internal registers if this value is
0xF0. Otherwise, it generates a dummy Acknowledge signal to terminate the cycle.
This was implemented to accommodate the G-Bus specifications.
System Reset input signal from the TX7901 to the Timer. This Active Low signal,
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when asserted, resets all three timer units simultaneously.
Disable Signal input from the TX7901 to the Timer. This Active Low signal, when
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asserted, allows the timers to be tested in the stand-by and multiplex modes. This
signal is currently hardwired to always be deasserted.
Test Signal input from the TX7901 to the Timer. This Active High signal, when
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asserted, allows a preset count data value to be written to the TMTRR register.
Currently, this signal is hardwired to always be deasserted.
External Clock input for Timer 1 from a source external to the TX7901. This clock may
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be used instead of the internal clock for counting or for pulse generation, and may be
divided internally before use.
External Clock input for Timer 2 from a source external to the TX7901. This clock may
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be used instead of the internal clock for counting or for pulse generation, and may be
divided internally before use.
Scan Test input from the TX7901 to the Timer. When asserted, this Active Low signal
causes the timers to be in the scan test mode. When the scan test mode is not used,
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this signal must be deasserted. This signal is currently hardwired to always be
deasserted.
Active Low acknowledge signal from the Timer. This signal is connected to the
gout04Ack32* signal of the G-Bus to indicate that a read or write operation from/to the
timer is complete. When the G-Bus master initiates a read or a write cycle to the
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timer, the timer responds by asserting this signal to indicate that the operation is
complete. In the event that the master sends a read or write request with Byte
Enables other than 0xF0, the timer will assert this signal (dummy acknowledgement)
to terminate the cycle, and will not read or write from/to its registers.
Active Low output for Timer 0 when it is configured as a Periodic Interval Timer. Timer
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0 is configured as a Periodic Interval Timer by writing to its configuration register. This
Description
10-4
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