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7.6.28
G-Bus Arbiter Master Status Register
This register indicates the status of the current G-Bus Master. When a master is granted bus
ownership, the Bus Broken Timer starts to count down. If the counter counts down to zero
before the arbiter receives the gbsgHaveIt signal, the corresponding bit is set and an
interrupt is generated to the C790. These bits are only cleared by the Reset signal.
63
31
Table 7-31 G-Bus Arbiter Master Status Register Fields
Bits
Field
63:16
–
15:0
Stat[15:0]
7.6.29
G-Bus Arbiter Control Register
The Control Register enables/disables granting the ownership of G-Bus to G-Bus masters.
63
31
Bit(s)
Field
63:16
–
15:1
GEn[15:1]
0
GEn[0]
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 7: C790 Bus/G-Bus Bridge
0
16
R/W
Reserved. Must be written as zeroes, and returns
R/O
zeroes when read.
G-Bus Master Status
R/O
0: Normal
1: Broken
0
16
Table 7-32 G-Bus Arbiter Granted Register Fields
R/W
Reserved. Must be written as zeroes, and returns zeroes
R/O
when read.
G-Bus Grant Enable
R/W
1: Enable Grant.
0: Do not enable Grant.
G-Bus Grant Enable of the G-Bridge
R/O
1: Enable Grant.
0: Do not enable Grant.
0
32
16 15
Stat[15:0]
16
Description
0
32
16 15
GEn[15:1]
15
Description
7-24
32
0
Initial Value
0x0000
0x0000
32
0
1
1
Initial Value
0
15'b All "1"
1
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