Toshiba TX79 Series User Manual page 62

The following table is a register map of the individual modules. Please note that this table is
still under construction. See the tables in each relevant chapter for more information.
Name
TIReg1
RIMReg1
RIReg1
-
-
TPFTReg1 Transmit Pause Frame Timer Register
VLANReg1
TDPReg1 Transmit Frame Descriptor Pointer Register
RDPReg1 Receive Frame Descriptor Pointer Register
CDPReg1 Current Frame Descriptor Pointer Register
BusErrReg1
peMACC1
peMACT1
IPGReg1
NBTBReg1
peCLRT1
peMAXF1
pePNCT1
peTBCT1
LSAII1
LSAI1
peVLTP1
TBTCnt1 Total Bytes Transmitted Count Register
TGFTCnt1
MFTCnt1
BFTCnt1
TxFrame64_1
TxFrame127_1
TxFrame255_1
TxFrame511_1
TxFrame1K1
TxFrameGt1K1
MPFTCnt1
LFTCnt1
TCCnt1
LCCnt1
MCCnt1
SCCnt1
EDCnt1
TRECnt1
TUECnt1
-
TBRCnt1
TRFRCnt1
MFRCnt1
BFRCnt1
RxFrame64_1
RxFrame127_1
RxFrame255_1
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 4: Address Maps
Register Description
Transmit Interrupt Register
Receive Interrupt Mask Register
Receive Interrupt Register
Reserved
Reserved
VLAN Tag Register
Bus Error Address Register
Internal Test Register (peMACC)
Internal Test Register (peMACT)
Back-to-Back IPG gap0
Non Back-to-Back IPG gap0
Internal Test Register0 (peCLRT)
Internal Test Register0 (peMAXF)
Internal Test Register0(pePNCT)
Internal Test Register 0 (peTBCT)
Local Station Addr II
Local Station Addr I
Internal Test Register (peVLTP)
Total Good Frames Transmitted
Multicast Frames Transmitted
Broadcast Frames Transmitted
Frames Transmitted (TxFrame64)
Frames Transmitted (TxFrame127)
Frames Transmitted (TxFrame255)
Frames Transmitted (TxFrame511)
Frames Transmitted (TxFrame1K)
Frames Transmitted (TxFrameGt1K)
MAC Pause Frames Transmitted
Long Frames Transmitted
Total Collisions
Late Collision
Multiple Collision
Single Collision
Excessive Deferrals
Transmit Retry Errors
Transmit Underflow Errors
Reserved
Total Bytes Received
Total Readable Frames Received
Multicast Frames Received
Broadcast Frames Received
Frames Received (RxFrame64)
Frames Received (RxFrame127)
Frames Received (RxFrame255)
Address
0x1E00_6038
0x1E00_6040
0x1E00_6048
0x1E00_6050
0x1E00_6058
0x1E00_6060
0x1E00_6068
0x1E00_6070
0x1E00_6078
0x1E00_6080
0x1E00_6088
0x1E00_6100
0x1E00_6108
0x1E00_6110
0x1E00_6118
0x1E00_6120
0x1E00_6128
0x1E00_6130
0x1E00_6138
0x1E00_61A8
0x1E00_61B0
0x1E00_61C8
0x1E00_6200
0x1E00_6208
0x1E00_6210
0x1E00_6218
0x1E00_6220
0x1E00_6228
0x1E00_6230
0x1E00_6238
0x1E00_6240
0x1E00_6248
0x1E00_6250
0x1E00_6258
0x1E00_6260
0x1E00_6268
0x1E00_6270
0x1E00_6278
0x1E00_6280
0x1E00_6288
0x1E00_6290
0x1E00_6298
0x1E00_62A0
0x1E00_62A8
0x1E00_62B0
0x1E00_62B8
0x1E00_62C0
0x1E00_62C8
0x1E00_62D0
4-9
R/W Size(b)
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64
R/W 64