Figure 12-4 Fields Of Miim D; Figure 12-5 Imperfect Filtering Of; Address Filtering - Toshiba TX79 Series User Manual

12.3.3.2 MIIM Data Register
The MIIM data register is used in conjunction with the MIIM control register. When reading a
PHY register, data are written to this register by the PHY. When writing to a PHY register,
data from this register are written to the PHY. Upon the completion of reset, this register's
value is 0x0000_0000.
63
31
Table 12-32 MIIM Data Register Field Descriptions
Bit(s)
15:0
12.3.4

Address Filtering

The MAC supports 48-bit addresses in two separate address tables: the Perfect Table and
the Hash Table. Only one of these tables is active at any time. Depending on the bit settings
in RFCReg (see Table 12-9 and Table 12-10), the MAC could work in one of six address
filtering modes.
Figure 12-5 Imperfect Filtering of Incoming Frames
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 12: 10/100 IEEE802.3 Media Access Controller
0
16
Figure 12-4 Fields of MIIM Data Register
Field
PHY Data
The 16-bit data read from the PHY after an MIIM read. The
Pdata
16-bit data to be written to the PHY before an MIIM write.
[15:0]
This register should not be written to if the Busy bit in the
MIIM Control Register is 1
47
0
Destination Address
G
512-Bit Hash Table
I
0
32
16 15
Description
31
32-Bit CRC
1 Unicast Address
12-34
Pdata
16
9 8 0
32
0