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9.1.9
32-/64-bit G-Bus I/O
The DMAC supports 32-/64-bit G-Bus I/O using dynamic bus sizing. When the DMAC
initiates a G-Bus cycle, the I/O device communicates its device size through gAck32B and
gAck64B.
For 32-bit devices, the DMAC reads or writes data on the lower 32 bits of the G-Bus only.
9.1.10
Memory Byte Alignment Support
If the C790 bus memory start address is not quad-word aligned, the DMAC divides the
memory access into C790 bus Single operations followed by C790 bus Burst operations. If
the C790 bus memory end address is also not quad-word aligned, the DMAC finishes with a
single C790 bus Single operation. Figure 9-5 is an example of the cycle division in little
endian memory. In this example, the memory transfer is divided into a Single cycle, a Burst
cycle of 2 quad-words, two burst cycles of 8 quad-words, and then two single cycles.
FFFFFFFF0 Hex
8-QW Boundary
8-QW Boundary
8-QW Boundary
000000000 Hex
Figure 9-5 C790 Bus Unaligned Address Cycle Break Down
The same occurs in the case of G-Bus memory access. If the G-Bus memory start address
is not quad-word aligned, the DMAC divides the memory access into G-Bus Single
operations followed by G-Bus Burst operations. If the G-Bus memory end address is also
not quad-word aligned, the DMAC finishes with a G-Bus Single operation.
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 9: DMA Controller
1QW
Unaligned Address
Cycle Division
9-7
1QW
FFFFFFFF0 Hex
8-QW Boundary
8-QW Boundary
8-QW Boundary
000000000 Hex
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