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Bit(s)
Field
R/W
0
GBI
9.2.3
Source Address Registers (SAR0 - SAR7)
These eight registers contain the source addresses of the DMA operation in progress for
each of the eight DMA channels.
63
31
Table 9-5 Source Address Register Field Definitions
Bit(s)
Field
63:32
–
31:0
SA
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 9: DMA Controller
Default
0: The interrupt bit is cleared.
1: The interrupt bit is ignored.
G-Bus Error Interrupt
If there is a G-Bus error interrupt, the DMAC will finish the pending DMA
transfer and stay idle until the G-Bus error interrupt is cleared. In this
state, the DMAC will stay idle even if the G-Bus error interrupt is masked
(GBIE=0).
When reading, this bit means the following:
R/W
0
0: No G-Bus error interrupt.
1: G-Bus error interrupt pending.
When writing, this bit means the following:
0: The interrupt bit is cleared.
1: The interrupt bit is ignored.
SA[31:0]
R/W
Default
R/O
0
Reserved
Source Address - SA[31:0]
For each DMA read cycle from the source device, the source
address is updated depending on the Source Device Counting
R/W
0
Mode (SCM). If the channel is programmed in the Chain Mode
(CHN = 1), the source address is loaded from the address
pointed to by the Next Record Pointer Register when a whole
block of data has been completely transferred.
Description
0
32
32
Description
9-14
32
0
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