Receive Descriptors - Toshiba TX79 Series User Manual

The buffer address must be 8-byte aligned while the Descriptor address must be 16-byte
aligned.
12.4.2

Receive Descriptors

The format of the Receive Descriptors is shown below. It is made of two double-words, and
the fields are described in more detail in Table 12-34.
63
OWN Byte-Count Buffer 1
12.4.2.1 Receive Descriptor
The Receive Descriptor contains the receive frame status, the frame length, and the
Descriptor ownership information in the first word (Word 0). The 32 bits of two Receive
Buffer Addresses is in the second word (Word 1). Bits [31:0] in Word 0 are read only. Bits
[30:0] are valid only when RxEOF is set.
Table 12-34 Receive Descriptor Field Descriptions
Word 0 Fields
Bit(s) Field
63 OWN
62:59 -
58:48 Buffer1 Size
47:37 Buffer2 Size
36 RxERing
35 RxChain
34 RxSOF
33 RxEOF
32:31 –
30:20 RxFrmLen
19 RxNoCRC
18 RxDType
17 RxFF
16:15 RxFrmType
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 12: 10/100 IEEE802.3 Media Access Controller
Byte-Count Buffer 2
Buffer Address 1
Figure 12-7 Receive Descriptor Format
When set, indicates that the Descriptor is owned by the MAC. When reset, indicates that
the Descriptor is owned by the C790. MAC clears this bit either when it completes the
frame reception or when the buffers that are associated with this Descriptor are full.
Must be set to "0".
Indicates the size in bytes of the first data buffer. If this field is zero, the MAC ignores this
buffer and only uses buffer 2.
The buffer size should be a multiple of 8. If it is not, the least three bits are ignored.
Indicates the size in bytes of the second data buffer. If RxChain is set (Address Chained),
the MAC ignores this buffer and fetches the next Descriptor.
Receive End of Ring
When set, indicates that the Descriptor pointer has reached its final Descriptor, and the
MAC returns to the base address of the list, creating a Descriptor ring.
Second Address Chained
When set, indicates that the second address in the Descriptor is the next Descriptor
address rather than the second buffer address. If RxERing is set, then RxChain is
ignored.
Start of Frame
When set, indicates that this Descriptor contains the first byte of a frame.
End of Frame
When set, indicates that this Descriptor contains the last byte of a frame. If this bit is not
set, all frame status bits are invalid except the OWN bit.
Reserved
Receive Frame Length
Strip CRC
Receive Data Type
0 : External frame
1 : Internal loop-back frame
Receive Frame Filter Fail
When set, indicates that the frame failed the address recognition filtering. This bit can be
set only when the MAC is in the promiscuous mode (RxAll bit is set in RFCReg).
Receive Frame Type
Control Bits
Buffer Address 2
Description
12-38
0
Word 0
Status Bits
Word 1