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C/BE#
1001
1010
1011
1100
1101
1110
1111
*g2pCycleType.type[n] may only be set to the value 0x6 to perform a "memory read multiple" cycle
through G2pWindow[n]. A write through G2pWindow[n] with g2pCycleType.type[n] set to 0x6 will result in
the PGB issuing a single DAC cycle with no data phase. This is an unsupported PCI transaction and may
produce unexpected results. Value 0b111 in type[n] is for cache operation, which requires careful
consideration of the cache configuration over the entire system.
8.2.7 Lower Address Bits
For RAM access, the G-Bus address bits gbsgAddr[1:0] are always forced to 0, and during
RAM burst transactions, linear sequential addressing is always performed. For RAM
transactions, PGB ensures that these lower bits are transmitted as "0" in both directions.
8.2.8 G-Bus to PCI Address Mapping, Addition method
The PGB performs G-Bus to PCI address mapping using the mechanism shown below. The
g2pLower and g2pUpper registers hold the lower and upper limits of the windows. These
limits lie on double-word boundaries. For example, if the limits of one window are addresses
0x1000 – 0x1400, the lower limit of the next window can be as close as 0x1400. The first
window will pass data up to byte 0x13FF inclusive.
gaddr
gpupper
gplower
gptarget
base
gpCycTyp
Figure 8-8 G-Bus to PCI Address Mapping, Addition method
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 8: PCI/G-Bus Bridge
Transaction Type
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual-Address Cycle
Memory Read Line
Memory Write and Invalidate
Repeated 4 times
GE
LE
+
+
-
/40
/4
PCI Space
PCI to G-Bus
No
Yes
Yes
Yes
Yes
Yes
Yes
/4
+
Logic
Master.cmd[3:0]
gbus R/W
8-12
G-Bus to PCI
Yes
Yes
Yes
Yes*
No*
Yes*
Yes*
hit
T
O
P
C
I
M
a
s
t
e
r
I
n
t
e
Master Addr[39:0]
r
f
a
c
e
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