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12.3.1.4 Transmit Status Register (TSReg)
The Transmit Status register is updated after a frame is fully transmitted or the transmission
of a frame is aborted due to an error. The register can be read to determine if the frame was
successfully transmitted or to determine what errors occurred. Upon the completion of reset,
this register's value is 0x0000_0000.
31
30
Tx
TxState[2:0]
FBE
1
15
14
13
TxFrm
0
Type
1
2
Bit(s)
Field
31
TxFBE
TxState
30:28
[2:0]
27:15
–
14:13
TxFrmType
12
TxExDefer
11
TxDefer
10
TxSCol
9
TxMCol
8
TxExCol
7
TxLCol
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 12: 10/100 IEEE802.3 Media Access Controller
28 27
3
12
11
10
9
TxEx
Tx
Tx
Tx
Defer
Defer
SCol
MCol
1
1
1
1
Table 12-11 TSReg Register Field Descriptions
R/W
Fatal Bus Error (0)
R/W
When set, indicates that a bus error occurred, and the MAC disables all of its bus access
operations.
Transmission Process State (000)
000 : Idle, TxEnable is 0
001 : Waiting, FIFO is empty or data is less than TxSOFTh (in TCReg)
010 : Waiting, Descriptor is not available
R/W
011 : Stopped, TxStart is reset to zero or Transmit Error occurred and TxEnHalt is set
100 : Suspended, Descriptor is not available
101 : Running, waiting for end of transmission
110 : Running, waiting for end of transmission and next Descriptor is not available
111 : Reserved
R/O
Reserved (0x000, 0)
Transmit Frame Type (00)
00 Ethernet (RFC 894 encapsulation)
R/W
01 IEEE802.2 (RFC 1042 encapsulation)
10 VLAN I
11 VLAN II
Excessive Deferral (0)
When set, indicates that the transmission was aborted because of an excessive deferral as
R/W
defined by the Defer bit in the transmit frame configuration register. This bit is not valid for full-
duplex.
Deferred (0)
When set, indicates the frame transmission was delayed because of a deferral. This bit is set
R/W
when a packet is transmitted with a collision and the standard back-off is selected in the
configuration register. This bit is not valid while the port is configured for full-duplex.
Single Collision (0)
R/W
When set, indicates that the packet being transmitted collided only once and was then
transmitted successfully on the Ethernet.
Multiple Collisions (0)
R/W
When set, indicates that the packet being transmitted collided more than once and was then
transmitted successfully on the Ethernet.
Collision Error (0)
R/W
When set, indicates that the packet transmission was aborted because of too many collisions.
The number of collision retries allowed is specified in the transmit frame configuration register.
R/W
Late Collision (0)
0
12
8
7
6
5
Tx
Tx
Tx
SQE
ExCol
LCol
LCar
1
1
1
1
Description
12-14
4
3
2
1
HW
Tx
Tx
Tx
FDup
Und
NoBuf
PStop
Sel
1
1
1
1
16
0
Tx
Good
1
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