Tsei Status Register (Sesr) - Toshiba TX79 Series User Manual

SER1, SER0: TSEI Bit Rate Select
The following table shows the relationship between the SER1 and SER0 control bits and the
bit rate for transfers when the TSEI is operating as a master. When the TSEI is operating as
a slave, the serial clock is input from the master; therefore, the SER1 and SER0 control bits
have no meaning.
15.8.2

TSEI STATUS REGISTER (SESR)

This register, which may be read or written to at any time, is used to indicate the current
state of the TSEI system and is used to switch between the TSEI operation modes. The
status flags can be cleared only in the Toshiba Mode by writing a "1" to them. Writing a "0"
value to these flags has no effect.
SEF
Comp. Mode
Toshiba Mode
Reset:
SEF: TSEI Transfer Complete Flag
Compatibility Mode:
This flag is automatically set to "1" at the end of a TSEI transfer. SEF is automatically
cleared by reading the SESR register with the SEF bit set.
Toshiba Mode:
Switching to the Toshiba Mode clears this flag. This flag always reads as "0," and writes to
this flag have no effect.
WCOL: Write Collision Error Flag
Compatibility Mode:
This flag is automatically asserted if the SEDR register is written to while a transfer is in
progress. The write itself has no effect on the running transmission. The WCOL flag is
automatically cleared by reading the SESR register with the WCOL bit set, then accessing
the SEDR register. No interrupt will be generated when asserting this flag.
Toshiba Mode:
The flag can only be reset by writing a "1" value to it. Writing a "0" has no effect. An interrupt
will be generated on TSIC0 on a transition from "0" to "1" if the module is configured as a
slave and TASM is equal to "0."
SOVF: Slave Mode Overflow Error
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 15: Serial Port Interface
SER1 SER0
0 0
0 1
17 0
1 1
7 6 5
WCOL SOVF
R R R
– R/C R/C
0 0 0
TSEI Clock Divided By
2
4
8
32
4 3
MODF TSRC TSTC
R –
R/C R/C R/C
0 0
15-13
2 1 0
TASM TMSE
– R/W R/W
R/W R/W
0 0 0
1
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