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11.1 Introduction
The Interrupt Controller arbitrates all the interrupt requests from internal and external
devices and sends the interrupt request that was granted access to the processor. The
interrupt controller features are:
32 internal and external interrupt requests
Interrupt mask
Level trigger only
11.2 Operation
The interrupt controller contains an interrupt status register to identify up to 16 different
interrupt sources. There is a corresponding 16-bit interrupt mask register. When the
corresponding mask bit is cleared, the interrupt request is disabled. Once an interrupt
request is detected and its corresponding mask bit is set, an interrupt request is asserted to
the C790.
Table 11-1 lists all the maskable interrupt sources.
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 11: Interrupt Controller
Table 11-1 Maskable Interrupt Sources
Interrupt Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
11-1
11. Interrupt Controller
Interrupt Source
G-Bridge
PCI-0
MAC0
MAC1
Reserved
DMAC
Timer0
Timer1
Timer2
UART0
UART1
SPI
PCI-1
External Interrupt Mac0
External Interrupt Mac1
External Interrupt 0
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