Table of Contents
Advertisement
8.3.2.3
PCI to G-Bus Memory Windows
The PCI accesses G-Bus locations through PCI memory windows called p2gwindows. Each
p2gwindow is defined by the normal PCI base register mechanism. The PGB provides four
PCI base registers; three DAC memory base pairs, and a single I/O base. These PCI base
registers allow for four individual p2gwindows. An additional register called p2gBase
provides the base address of the G-Bus transaction performed.
8.3.2.3.1 p2g Base Address Registers (p2gBase)
When a G-Bus cycle is initiated, p2gBase is added to the PCI offset address to produce the
effective G-Bus address. G-Bus access to these registers is allowed using the G-Bus single
cycle mode.
The p2g Base Address Register fields are detailed below and in Table 8-13.
63
31
Table 8-13 p2gBase Address Register Field Descriptions
Bits
Field
63:32
31:3
p2gBase
2:0
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 8: PCI/G-Bus Bridge
32
p2gBase [31:3]
29
R/W
–
R/O
Reserved. Read back at "0". (0)
R/W
Address used for base of G-Bus transaction. Cleared on reset. (0)
–
R/O
Reserved. Read back as "0". (0)
0
Description
8-26
32
3
2
0
0
3
Advertisement
Table of Contents
