Table of Contents
Advertisement
8.3.2.1
PGB Control and Status Register (pgbCSR )
The pgbCSR Register provides overall control and status for the PGB. Ten bits provide
control and status. Bits[23:16] are the latency timer for G-Bus delayed reads. G-Bus Access
to this register is allowed using the G-Bus single cycle mode.
63
31
24 23
0
8
Table 8-7 PGB Control and Status Register Field Descriptions
Bit(s)
Field
R/W
63:24
–
R/O
23:16
Lt[7:0]
R/W
15
–
R/O
14
Res
R/W
13
Orp
R/W
12
Bes
R/O
11
Bec
R/W
10
Pfr
R/W
9
Wer
R/W
8
Ger
R/W
7:5
–
R/O
4
Eor
R/W
3
Arb
R/W
2
Hst
R/W
1
Enp
R/W
0
Eni
R/W
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 8: PCI/G-Bus Bridge
16
15
14 13
R
O
Lt[7:0]
0
E
R
S
P
8
1
1
1
Reserved. Returns "0" when read. (0)
Latency Timer: 8-bit latency timer for G-Bus delayed reads to PCI. (8'h30)
Reserved. Returns "0" when read. (0)
PCI Reset: This bit is set when a PCI Reset occurs and the incoming PCI RST input causes
a reset. This bit is cleared by a system reset (G-Bus reset) or by writing a "1" to it. (0)
Orphan: This bit is set when a G-Bus Master does not return to complete a delayed read,
causing an orphaned read interrupt. Cleared during reset or by writing a "1" to it. (0)
Bell Set: writing a "1" to this bit sets the Bec status bit and generates an interrupt. This bit
always reads as "0". (0)
Bell Clear: Set when a one is written to the Bes bit. Cleared during reset or by writing a "1" to
it. (0)
PCI Error: Set when a PCI Parity or Fatal error takes place during a PCI transaction with a G-
Bus Master. PGB interrupt is generated when an error occurs. Cleared during reset or by
writing a "1" to it. (0)
Window Error: Set when G-Bus Master attempts to cross a g2pWindow. Cleared during reset
or by writing a "1" to it. (0)
G-Bus error: Set by PGB Master on GBUSERR#. Cleared during reset or by writing a "1" to it.
(0)
Reserved. Returns "0" when read. (0)
Enables Orp provided that Eni does not override Eor. Enables the Orphan interrupt when set.
Eni, when cleared, overrides this bit and Orp is disabled regardless of Eor status. Set to "1"
during reset. (0)
Arbiter: Enables the Arbiter. The Arbiter is unaffected by the condition of the other bits. Set to
"1" during reset. The contents of this bit should only be changed during PCI Reset. (0)
Host Mode: Set this bit to "1" for Host Mode of operation or clear it for Satellite Mode
operation. Cleared during G-Bus reset. During PCI Reset, the application should set this bit to
"1" to configure the core to perform Host functions, or set this bit to "0" to configure the core
to behave as a Satellite. This bit should not be changed dynamically by the application, which
could cause the system to read the wrong PCI configuration space and disable certain
operations. (0)
Enable PGB: Enables G-Bus transactions involving g2pWindows. Reading this command is
equivalent to reading pciCommand[2]. Cleared during reset. (0)
Enable Interrupts: Enables PGB interrupts. Overrides the Eor bit when cleared. Set to "1"
during reset. (0)
0
32
12
11
10
9
8 7
B
B
P
W
G
E
E
F
E
E
0
S
C
R
R
R
1
1
1
1
1
3
Description
8-21
32
5 4
3
2
1
0
E
A
H
E
E
O
R
S
N
N
R
B
T
P
I
1
1
1
1
1
Advertisement
Table of Contents
