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Signal Name
tmrgInt1B
tmrgInt2B
TIMOUT1*
TIMOUT2*
tmrwdtreq2B
tmrgdata[63:0]
10.4 Configuration Registers
Table 10-3 lists the addresses of the registers that configure the operation of the three
TX7901 Timer/Counters when written to. Detailed descriptions of the fields of each of these
registers appear in the following sub-sections. Register functionality and operation is
discussed in Section 10.5 in addition to discussing Timer/Counter Operation.
Register Name
Timer Control Register
Timer Interrupt Status Register
Compare Register A
Compare Register B
Interval Timer Mode Register
Divider Register
Pulse Generator Mode Register
Watch Dog Timer Mode Register
Timer Read Register
Note: Accessing registers that are marked "Reserved" will result in unknown behavior. All registers must be accessed
as 32-bit quantities.
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 10: Programmable Timer/Contents
I/O
output is connected to Interrupt 6 of the Interrupt Controller. This output will be
asserted when the Max Count is reached, and will remain asserted until the proper
registers are written to (to de-assert it), or until the C790 is Reset.
Active Low output for Timer 1 when it is configured as a Periodic Interval Timer. Timer
1 is configured as a Periodic Interval Timer by writing to its configuration register. This
O
output is connected to Interrupt 7 of the Interrupt Controller. This output will be
asserted when the Max Count is reached, and will remain asserted until the proper
registers are written to (to de-assert it), or until the C790 is Reset.
Active Low output for Timer 2 when it is configured as a Periodic Interval Timer. Timer
2 is configured as a Periodic Interval Timer by writing to its configuration register. This
O
output is connected to Interrupt 8 of the Interrupt Controller. This output will be
asserted when the Max Count is reached, and will remain asserted until the proper
registers are written to (to de-assert it), or until the C790 is Reset.
Active Low output of Timer 1 when it is configured as a Pulse Generator. This output
is exclusively used by devices outside of the TX7901. It is connected to an I/O pad
O
output buffer for this purpose. Both the duty cycle and the frequency of the pulse
generated on this output are programmable by writing appropriate values to the
respective timer's configuration registers.
Active low output of Timer 2 when it is configured as a Pulse Generator. This output is
exclusively used by devices outside of the TX7901. It is connected to an I/O pad
O
output buffer for this purpose. Both the duty cycle and the frequency of the pulse train
generated from this output are programmable by writing appropriate values to the
respective timer's configuration registers.
Active Low output of Timer 2 when configured as a Watchdog Timer. This output is
O
demultiplexed onto either the NMI input or the Master Reset input of the TX7901, and
the demultiplexer is controlled by bit 16 of the Watchdog Mode Register.
Data bus output from the Timer to the G-Bus. The Timer drives this bus to
O
0xFFFF_FFFF when there are no data to output to the G-Bus. In other cases, the
Timer only drives bits [31:0] of this bus.
Table 10-3 Timer/Counter Configuration Registers
Timer 0
R/W
Address
R/W
0x1E00_4000
R/W
0x1E00_4004
R/W
0x1E00_4008
R/W
0x1E00_400C
R/W
0x1E00_4010
R/W
0x1E00_4020
R/W
Reserved
R/W
Reserved
R/O
0x1E00_40F0
Description
Timer 1
Field
Address
Name
TMTCR0
0x1E00_4100
TMTISR0
0x1E00_4104
TMCPRA0
0x1E00_4108
TMCPRB0
0x1E00_410C
TMITMR0
0x1E00_4110
TMCCDR0
0x1E00_4120
Reserved
0x1E00_4130
Reserved
Reserved
TMTRR0
0x1E00_41F0
10-5
Timer 2
Field
Address
Name
TMTCR1
0x1E00_4200
TMTISR1
0x1E00_4204
TMCPRA1
0x1E00_4208
TMCPRB1
0x1E00_420C
TMITMR1
0x1E00_4210
TMCCDR1
0x1E00_4220
TMPGMR1
0x1E00_4230
Reserved
0x1E00_4240
TMTRR1
0x1E00_42F0
Field
Name
TMTCR2
TMTISR2
TMCPRA2
TMCPRB2
TMITMR2
TMCCDR2
TMPGMR2
TMWTMR2
TMTRR2
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