Tsei S Ystem E Rrors - Toshiba TX79 Series User Manual

When the TSEI system is enabled as a master, bit 3 in the DDCR register must be set to "1"
to enable the master serial data output. If a master device needs to initiate a TSEI transfer
to receive a byte of data from a slave without transmitting a byte, it might purposely leave
the TSDMOSI output disabled.
TSEI systems that tie TSDMOSI and TSDMISO together to form a single bi-directional data
line also need to selectively disable the TSDMOSI output.
TSDMISO: Master Input, Slave Output
When the TSEI system is enabled as a slave, bit 2 in the DDCR register must be set to "1"
to enable the slave serial data output. A master TSEI device can simultaneously broadcast a
message to several slaves as long as no more than one slave tries to drive the TSDMISO
line. TSEI systems that tie TSDMOSI and TSDMISO together to form a single bi-directional
data line also need to selectively disable the TSDMISO output.
When the TSEI system is enabled as a master, the TSDMISO pin acts as the master serial
data input, regardless of the state of this bit.
15.9 TSEI System Errors
TSEI is only used in the Slave Mode, and therefore does not report any errors.
15.10 Interrupt Generation
Interrupt processing differs for the two TSEI operating modes, which can be selected using
the TMSE bit in the SESR register. The TSEI module is connected to three interrupt
channels named TSIC0, TSIC1, and TSIC2.
15.10.1 Compatibility Mode
In the Compatibility Mode, only TSIC Channel 0 is used. This channel generates an interrupt
if either the SEF flag or the MODF flag in the SESR register shows a transition from "0" to
"1." The SEIE bit is used as a global interrupt enable/disable.
TSEI Interrupt Channel 0 (TSIC0)
TSEI Interrupt Channel 1 (TSIC1)
TSEI Interrupt Channel 2 (TSIC2)
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 15: Serial Port Interface
Interrupt on MODF or SEF
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