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The DAL address register (AR) is a register that specifies the program-memory-indirect when the DALR instruction is
executed with the 16-bit register.
There are two types of commands that load the program memory data: the DAL instruction and the DALR instruction.
For the DAL instruction, the contents of the (six-bit) ADDR3 in the operand and of the general register (r) become the
reference address of the program memory. For the DALR instruction, the 14 bits of the DAL address register become the
reference addresses. When the DAL instruction is executed, the program memory area (0000H ~ 03FFH) becomes the
reference area. All the areas in the program memory area can be referred to by executing the DALR instruction. Whenever
the DALR instruction is executed, the content of the DAL address register is increased by +1. Therefore data can be
continuously loaded.
Moreover, the content of the data register can be transmitted to the DAL address register in 14 bits with one instruction
by executing the MVAR instruction.
The contents of the DAL address register can be accessed in four-bit units on execution of an OUT1/IN1 instruction for
which [CN = 1H] is specified in the operand. DAL address register port is divided and indirectly specified with the data
selection port (φL1A) and set. The data of the specified port to be set beforehand is set and the data port corresponding to it
is accessed. Each time the data select port (φL/K11) is accessed it is increased by +1. Therefore the data can be continuously
accessed after setting up a data selection port.
Note: The DAL address register is valid only when the DALR instruction is executed, and is ineffective when
any other instruction is executed. Moreover, the DAL address register is unaffected by the DAL
instruction.
Note: This product has 8 k steps of ROM capacity; if 2000H ~ 3FFFH is specified in the DAL register and the
DALR instruction is executed, the contents of the data register will become indeterminate.
Note: It is possible to rewrite and reference the contents of the interrupt stack registers ISRd0~ISRd15
( φ L/K10(C ∼ F)) through programming.
3. Carry flag (φL/K1B)
The carry flag is set when either Carry or Borrow occurs in the result of the calculation instruction execution and is reset
if neither of these occurs. This carry flag is accessed with an OUT1/IN1 instruction for which [CN = BH] has been specified.
The carry flag contains a four-level interrupt stack register. When an interrupt is issued, this bit is evacuated to the
interrupt register specified by the interrupt stack pointer, and is returned with the RNI instruction.
φL/K10(6)
Y1
ISP0
Interruption stack pointer
Y2
Y4
Y8
ISP1
*/0
*/0
Interrupt stack pointer
φL/K10(B)
Page
Page
ISRCA
0
1
2
3
Interruption stack register
Interrupt stack register
At the time of interruption
At the time of interrupt
processing execution
processing execution
Y1
φ L/K1B
Ca
44
*/0
*/0
*/0
At the time of RNI
instruction execution
Y2
Y4
Y8
*/0
*/0
*/0
Carry flag
Carry flag
TC9349AFG
2006-02-24
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