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8.3.2.2.3 g2pBase Address Registers (g2pBase0, g2pBase1, g2pBase2, g2pBase3)
The functionality of these registers is described in Section 8.3.2.2 above. The fields of these
registers are further detailed in the following figure and Table 8-10.
63
31
Table 8-10 g2pBase Address Register Field Descriptions
Bit(s)
Field
63:3
g2pBase
2:0
–
8.3.2.2.4 g2pCycleType Register (g2pCycleType)
When a PCI cycle is initiated, g2pCycleType is used to define which of the 15 possible PCI
cycle types are performed. G-Bus access to this register is allowed using the G-Bus single
cycle mode.
31
29
28
0
e[3]
3
1
15
13
12
0
e[1]
3
1
Table 8-11 g2pCycleType Register Field Definitions
Bit(s)
Field
31:29
–
28
e[3]
27
–
26:24
type[3]
23:21
–
20
e[2]
19
0
18:16
type[2]
15:13
–
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 8: PCI/G-Bus Bridge
g2pBase [63:32]
32
g2pBase [31:3]
29
R/W
R/W
Address used for base of PCI transaction. Cleared during reset. (0)
R/O
Reserved (0)
27
26
24 23
0
type[3]
1
3
11
10
8
7
0
type[1]
1
3
R/W
R/O
Reserved. Read back as "0". (0)
R/W
Enable for g2pWindow[3]. Cleared during reset. (0)
R/O
Reserved (0)
Assigned to PCI C/BE[3:1]* during PCI address phase through
R/W
g2pWindow[3]. Cleared during reset. (0)
R/O
Reserved. Read back as "0". (0)
R/W
Enable for g2pWindow[2]. Cleared during reset. (0)
R/O
Reserved (0)
Assigned to PCI C/BE[3:1]* during PCI address through g2pWindow[2].
R/W
Cleared during reset. (0)
R/O
Reserved. Read back as "0". (0)
8-24
3
Description
21
20
19
18
0
e[2]
0
3
1
1
5
4
3
2
0
e[0]
0
3
1
1
Description
32
2
0
0
3
16
type[2]
3
0
type[0]
3
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