Table of Contents
Advertisement
10.4.5
Watchdog Timer Mode Register (TMWTMR) Fields
The following figure and Table 10-8 detail the fields of the Watchdog Timer Mode Register,
TMWTMR.
31
15
14
T
W
I
E
1
Table 10-8 Watchdog Timer Mode Register (TMWTMR) Field Descriptions
Bit(s)
Field
Field Name
31:17
–
Watchdog Output
16
WDOS
Watchdog Timer
15
TWIE
Interrupt Enable
14:8
–
Watchdog Timer
7
WDIS
6:1
–
Watchdog Timer
0
TWC
Note: The register fields marked "Reserved" are read back as zeroes, and are ignored when written to.
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 10: Programmable Timer/Contents
0
15
8
0
7
R/W
–
R/O
Reserved
Selects the type of exception to issue when the Watchdog Timer expires.
(0)
R/W
0 : Causes an NMI.
Select
1 : Causes a Master Reset
(The default value is "0.")
Sets interrupt enable/disable in the Watchdog Timer Mode. (0)
R/W
0: Disable (mask)
1: Enable
–
R/O
Reserved
Disables the Watchdog Timer Mode when WDIS is set to "1" and then sets
the TCE bit of the timer control register to "0". (0)
R/W
Disable
Note: The WDIS bit will automatically be cleared to "0" after the watchdog
timer is disabled. Writing 0 to the WDIS bit has no effect
–
R/W
Reserved
1: Clears the Watchdog Timer's counter. (0)
R/W
Note: The TWC bit will be automatically cleared to "0" after the counter is
Clear
cleared. Writing 0 to the TWC bit has no effect.
7
6
W
D
0
I
S
1
6
Description
10-10
16
W
D
O
S
1
1
0
T
W
C
1
Advertisement
Table of Contents
