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SIGNAL
TYPE
gbsgLastB
urtgAck32B
urtgData[63:0]
Serial Interface (Two sets)
BAUD
RCLK
RCLK_BAUD
SIN
SOUT
DCD*
RI*
DSR*
CTS*
OUT2*
OUT1*
RTS*
DTR*
DMAC Interface
urtgRxRdyB
urtgTxRdyB
G-Bus Bridge Interface
urtgIntB
Note: Active Low external signals are indicated by a suffix of "*" (asterisk), or "B" (Capital B) for
Active Low internal TX7901 signals.
14.4
UART Device Register Description
This section describes the block of device registers that control each UART. There are two
of each of the device registers described in this section, one for each of the UARTs. Each
type of register is located at the same offset position in both UART channels' blocks of
device registers.
14.4.1
UART Device Register Addressing
Most of the UART device registers are directly addressed through the address lines. One of
the following four register types is accessed: the Divisor Latch Registers, the Receive Buffer
Register, the Transmit Holding Register, or the Interrupt Enable Register. The register to be
accessed is selected according to the following: the setting of bit 7 (the Divisor Latch
Address Bit, DLAB) of the respective Line Control Register, and whether one is reading from
or writing to the accessed register. (Please refer to Table 14-2 and Table 14-3).
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 14: UARTS WITH FIFOS
Input
The G-Bus Master asserts this signal to indicate the last transaction.
G-Bus Acknowledge. UART asserts this signal to acknowledge a 32-bit width
Output
read/write transfer.
Output
64-bit read data from UART to G-Bus
Receive/Transmit clock, derived from CLK. Divided by the value in the divisor latch
Output
DLL & DMM.
Input
Receive Clock
RCLK Select. When tied hHigh, RCLK is connected internally to BAUD; when tied
Input
Low, the RCLK pin is used as the Receive clock.
Input
Serial Input. Data are clocked in using RCLK/16.
Serial Output. Data are clocked out using the output from the Baud Rate Generator,
Output
then divided by 16.
Input
Data Carrier Detect, MSR[7] status bit. Active Low
Input
Ring Indicator, MSR[6] status bit. Active Low
Input
Data Set Ready, MSR[5] status bit. Active Low.
Input
Clear To Send, MSR[4] status bit. Active Low
Output
General Control, MSR[3] control bit. Active Low
Output
General Control, MSR[2] control bit. Active Low
Output
Request To Send, MSR[1] control bit. Active Low
Output
Data Terminal Ready, MSR[0] control bit. Active Low
Output
DMA Handshake. Goes Low when RX FIFO contains data.
Output
DMA Handshake. Goes Low when TX FIFO is empty.
Interrupt Request. Goes Low whenever one of the enabled interrupts becomes valid.
Output
This signal goes to the interrupt controller inside the G-Bus Bridge.
DESCRIPTION
14-4
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