Toshiba TX79 Series User Manual page 227

Bit(s) Field
7 TxC511
6 TxC255
5 TxC127
4 TxC64
3 TxCBC
2 TxCMC
1 TxCFrm
0 TxCByte
12.3.1.8 Receive Interrupt Mask Register (RIMReg)
The bits of the Receive Interrupt Mask Register enable the corresponding interrupt bits of
the Receive Interrupt Register to cause an interrupt. When a receive event occurs or a
counter overflows, it sets one of the bits in the Receive Interrupt Register, and the macgIntB
signal becomes active if the corresponding enable bit in this register is set to 1. When any
bit in this register is 0 and the corresponding bit is set to 1 in the Receive Interrupt Register,
it is masked (hidden), preventing it from driving the macgIntB signal and causing an interrupt.
Upon the completion of reset, this register's value is 0x0000_0000.
31
15 14 13 12
RxC RxC RxC
RxC
Unds NoAln CRC
ErrM
M M M
1 1 1
Bit(s) Field
31:25
24 RxFBErrM
23 RxStopM
22 RxReadFrmM
21 RxBufErrM
20 RxFOverfM
19 RxCNoFiFM
18 RxCNoDesM
17 RxCJabM
16 ExCFragM
15 RxCUndsM
14 RxCNoAlnM
13 RxCCRCM
12 RxCErrM
11 RxCLongM
10 RxCPauseM
9 RxCGt1KM
8 RxC1KM
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 12: 10/100 IEEE802.3 Media Access Controller
R/W
R/W Frames Transmitted (256~511 byte) Counter Overflow (0)
R/W Frames Transmitted (128~255 byte) Counter Overflow (0)
R/W Frames Transmitted (65~127 byte) Counter Overflow (0)
R/W Frames Transmitted (64 byte) Counter Overflow (0)
R/W Broadcast Frames Transmitted Counter Overflow (0)
R/W Multicast Frames Transmitted Counter Overflow (0)
R/W Total Good Frames Transmitted Counter Overflow (0)
R/W Total Bytes Transmitted Counter Overflow (0)
25
0
7
11 10 9
RxC
RxC RxC
Gt1K
Long Pause
M M
M
1 1 1 1
Table 12-15 RIMReg Register Field Descriptions
R/W
– R/O Reserved (0x00)
R/W Receive Fatal Bus Error Mask (0)
R/W Receive Stopped Mask (0)
R/W A Readable Frame received Mask (0)
R/W Truncated Frame due to no more Descriptor Mask (0)
R/W Receive FIFO Overflow Error Mask (0)
R/W No RxFIFO Missed Frames Counter Overflow Mask (0)
R/W No RxDescriptor Missed Frame Counter Overflow Mask (0)
R/W Jabber Frames Received Counter Overflow Mask (0)
R/W Fragments Received Counter Overflow Mask (0)
R/W Undersized Frames Counter Overflow Mask (0)
R/W Misaligned Frames Counter Overflow Mask (0)
R/W Frames Received with Bad CRC Counter Overflow Mask (0)
R/W Receive Errors Counter Overflow Mask (0)
R/W Long Frames Received Counter Overflow Mask (0)
R/W MAC Pause Frames Received Counter Overflow Mask (0)
R/W Frames Received (1024~max byte) Counter Overflow Mask (0)
R/W Frames Received (512~1023 byte) Counter Overflow Mask (0)
Description
24 23 22 21
Rx Rx Rx
RxFB
Stop Read Buf
ErrM
M FrmM ErrM
1 1 1 1
8 7 6 5
RxC
RxC RxC RxC
1KM 511M 255M 127M
1 1 1 1
Description
12-19
20 19 18 17
RxF RxC RxC
RxC
Overf NoFi No
JabM
M FM DesM
1 1 1 1
4 3 2 1
RxC RxC RxC RxC
64M BCM MCM FrmM
1 1 1 1
16
ExC
Frag
M
1
0
RxC
Byte
M
1