Toshiba TX79 Series User Manual page 269

14.4.5.4 FE – Framing Error
If the FIFOs are disabled, this bit is set if the received data did not have a valid STOP bit.
This bit is reset when the G-Bus reads this register.
If the FIFOs are enabled, the state of this bit is revealed to the G-Bus when the byte it refers
to is at the top of the FIFO.
14.4.5.5 BI – Break Interrupt
If the FIFOs are disabled, this bit is set whenever the SIN is held in the 0 state for more than
one transmission time (START bit + DATA bits + PARITY + STOP bits). It is reset by the G-
Bus that reads this register.
If the FIFOs are enabled, this error is associated with a corresponding character in the FIFO
and is flagged when this byte is at the top of the FIFO. When a break occurs, only one zero
character is loaded into the FIFO: the next character transfer is enabled when SIN goes into
the marking state and it receives the next valid start bit.
14.4.5.6 THRE – TX Holding Register Empty
If the FIFOs are disabled, this bit is set to "1" whenever the TX Holding Register is empty
and ready to accept new data and it is cleared when the data are transferred to the TX Shift
Register.
If the FIFOs are enabled, this bit is set to "1" whenever the TX FIFO is empty and it is
cleared when at least one byte is written to the TX FIFO.
14.4.5.7 TEMT – Transmitter Empty
If the FIFOs are disabled, this bit is set to "1" whenever the TX Holding Register and the TX
Shift Register are empty. If the FIFOs are enabled, this bit is set whenever the TX FIFO and
the TX Shift Register are empty. In both cases, this bit is cleared when a byte is written to
the TX data channel.
14.4.5.8 FIFOERR – RX-Data Error in FIFO
If the FIFOs are disabled, this bit is always set to "0". If the FIFOs are enabled, this bit is set
to "1" when there is at least one PE, FE, or BI in the RX FIFO. It is cleared by a read from
the LSR register provided there are no subsequent errors in the FIFO.
TX7901 User's Manual (Rev. 6.30T – Nov, 2001)
Chapter 14: UARTS WITH FIFOS
14-9