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Figure 3.
V
Overshoot Example Waveform
CC
VID + 0.050
VID - 0.000
NOTES:
1.
V
OS
2.
T
OS
2.6.4
Die Voltage Validation
Overshoot events on processor must meet the specifications in
across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in
duration may be ignored. These measurements of processor die level overshoot must
be taken with a bandwidth limited oscilloscope set to a greater than or equal to
100 MHz bandwidth limit.
2.7
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as V
separate power planes for each processor (and chipset), separate V
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see
GTL+ signals are provided on the processor silicon and are terminated to V
chipsets will also provide on-die termination, thus eliminating the need to terminate the
bus on the motherboard for most GTL+ signals.
26
Example Overshoot Waveform
0
5
T
V
is measured overshoot voltage.
is measured time duration above VID.
Table 15
for GTLREF specifications). Termination resistors (R
T
OS
10
15
Time [us]
: Overshoot time above VID
OS
: Overshoot above VID
OS
. Because platforms implement
TT
Electrical Specifications
V
OS
20
25
Table 8
when measured
and V
supplies
CC
TT
) for
TT
. Intel
TT
Datasheet
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