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2.2.57 SLEEP

SLEEP (SLEEP)
Operation
Program execution state → power-down mode
Assembly-Language Format
SLEEP
Operand Size
Description
When the SLEEP instruction is executed, the CPU enters a power-down state. Its internal state
remains unchanged, but the CPU stops executing instructions and waits for an exception-handling
request. When it receives an exception-handling request, the CPU exits the power-down state and
begins the exception-handling sequence. Interrupt requests other than NMI cannot end the power-
down state if they are masked in the CPU.
Available Registers
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
SLEEP
Notes
For information about the power-down state, see the relevant microcontroller hardware manual.
Condition Code
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Operands
1st byte
0
1
173
I
UI H
U
— — — — — — — —
Instruction Format
2nd byte
3rd byte
8
0
Power-Down Mode
N
Z
V
C
No. of
States
4th byte
2

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