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7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended
and added to the 24-bit program counter (PC) contents to generate a branch address. The PC value
to which the displacement is added is the address of the first byte of the next instruction, so the
possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes
(–16383 to +16384 words) from the branch instruction. The resulting value should be an even
number.
8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction specifies a memory operand by an 8-bit absolute address. This
memory operand contains a branch address. The upper 8 bits of the absolute address are assumed
to be 0 (H'00), so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to
H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the
branch address is 16 bits long. In advanced mode the memory operand is a longword operand. The
first byte is ignored and the branch address is 24 bits long. Note that the first part of the address
range is also the exception vector area. For further details see the relevant microcontroller
hardware manual.
Specified
by @aa:8
(a) Normal mode
Figure 1-13 Branch Address Specification in Memory Indirect Mode
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing access to be performed at the address preceding the
specified address. [See (2) Memory Data Formats in section 1.5.2 for further information.]
(2) Effective Address Calculation: Table 1-6 indicates how effective addresses are calculated in
each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in
order to generate a 16-bit address.
Branch address
Specified
by @aa:8
Branch address
(b) Advanced mode
30
Reserved
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