3) Divxs - Hitachi H8/300H Series Programming Manual

2.2.26 (3) DIVXS

DIVXS (DIVide eXtend as Signed)
DIVXS instruction, Division by Zero, and Overflow
Since the DIVXS instruction does not detect division by zero or overflow, applications should
detect and handle division by zero and overflow using techniques similar to those used in the
following program.
1. Programming solution for DIVXS.B R0L, R1
Example 1: Convert dividend and divisor to non-negative numbers, then use DIVXU
programming solution for zero divide and overflow
MOV.B R0L, R0L
BEQ ZERODIV
ANDC #AF, CCR
BPL L1
NEG.B R0L
ORC #10, CCR
L1: MOV.W R1.R1
BPL L2
NEG.W R1
XORC #50, CCR
L2: MOV.B R1H, R2L
EXTU.W R2
DIVXU.B R0L, R2
MOV.B R2H, R1H
DIVXU.B R0L, R1
MOV.B R2L, R2H
MOV.B R1L, R2L
STC CCR, R1L
BTST #6, R1L
BEQ L3
NEG.B R1H
L3: BTST #4, R1L
BEQ L4
NEG.W R2
L4: RTS
ZERODIV:
This program leaves a 16-bit quotient in R2 and an 8-bit remainder in R1H.
R1
R1H
R2
; Test divisor
; Branch to ZERODIV if R0L = 0
; Clear CCR user bits (bits 6 and 4) to 0
; Branch to L1 if N flag = 0 (positive divisor)
; Take 2's complement of R0L to make sign positive
; Set CCR bit 4 to 1
; Test dividend
; Branch to L2 if N flag = 0 (positive dividend)
; Take 2's complement of R1 to make sign positive
; Invert CCR bits 6 and 4
;
;
; Use DIVXU.B instruction to divide non-negative dividend
; by positive divisor
16 bits ÷ 8 bits → quotient (16 bits) and remainder (8 bits)
;
; (See DIVXU Instruction, Zero Divide, and Overflow)
;
; Copy CCR contents to R1L
; Test CCR bit 6
; Branch to L3 if bit 6 = 1
; Take 2's complement of R1H to make sign of remainder negative
; Test CCR bit 4
; Branch to L4 if bit 4 = 1
; Take 2's complement of R2 to make sign of quotient negative
; Zero-divide handling routine
R0L
Dividend
Remainder
Quotient
86
Divisor
Divide Signed