1) Shar (B) - Hitachi H8/300H Series Programming Manual

2.2.54 (1) SHAR (B)

SHAR (SHift Arithmetic Right)
Operation
Rd (right arithmetic shift) → Rd
Assembly-Language Format
SHAR.B Rd
Operand Size
Byte
Description
This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the right. Bit
0 shifts into the carry flag. Bit 7 shifts into itself. Since bit 7 remains unaltered, the sign does not
change.
MSB
b
7
Available Registers
Rd: R0L to R7L, R0H to R7H
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Register direct SHAR.B
Notes
. . . . . .
Operands
1st byte
Rd 1
Condition Code
I UI H
— — — —
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
cleared to 0.
Z: Set to 1 if the result is zero; otherwise
cleared to 0.
V: Set to 1 if an overflow occurs; otherwise
cleared to 0.
C: Receives the previous value in bit 0.
LSB
b C
0
Instruction Format
2nd byte 3rd byte
1 8 rd
164
Shift Arithmetic
U N Z V C
0
No. of
States
4th byte
2