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Table 2-2 Instruction Set (cont)
(2) Arithmetic Operation Instructions
Mnemonic
Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation
CMP
CMP.B #xx:8,Rd
B
2
CMP.B Rs,Rd
B
CMP.W #xx:16,Rd
W
4
CMP.W Rs,Rd
W
CMP.L #xx:32,ERd
L
6
CMP.L ERs,ERd
L
MULXU
MULXU.B Rs,Rd
B
MULXU.W Rs,ERd
W
MULXS
MULXS.B Rs,Rd
B
MULXS.W Rs,ERd
W
DIVXU
DIVXU.B Rs,Rd
B
DIVXU.W Rs,ERd
W
DIVXS
DIVXS.B Rs,Rd
B
DIVXS.W Rs,ERd
W
EXTU
EXTU.W Rd
W
EXTU.L ERd
L
EXTS
EXTS.W Rd
W
EXTS.L ERd
L
Addressing Mode and Instruction Length (bytes)
2
2
2
2
2
4
4
2
2
4
4
2
2
2
2
Rd8–#xx:8
Rd8–Rs8
Rd16–#xx:16
Rd16–Rs16
ERd32–#xx:32
ERd32–ERs32
Rd8 × Rs8→Rd16
(unsigned operation)
Rd16 × Rs16→ERd32
(unsigned operation)
Rd8 × Rs8 → Rd16
(signed operation)
Rd16 × Rs16 → ERd32
(signed operation)
Rd16 ÷ Rs8 → Rd16 (RdH: remainder, — — 6 7 — —
RdL: quotient) (unsigned operation)
ERd32 ÷ Rs16 → ERd32 (Ed: remainder, — — 6 7 — —
Rd: quotient) (unsigned operation)
Rd16 ÷ Rs8 → Rd16 (RdH: remainder, — — 8 7 — —
RdL: quotient) (signed operation)
ERd32 ÷ Rs16 → ERd32 (Ed: remainder, — — 8 7 — —
Rd: quotient) (signed operation)
0 → (<bits 15 to 8> of Rd16)
0 → (<bits 31 to 16> of ERd32)
(<bit 7> of Rd16) → (<bits 15 to
8> of Rd16)
(<bit 15> of ERd32) → (<bits 31 to 16> — —
of ERd32)
192
Condition Code
No. of States
Ad-
I
H
N Z V C
Normal vanced
—
2
2
—
2
2
— 1
4
4
— 1
2
2
— 2
4
6
— 2
2
2
— — — — — —
14
14
— — — — — —
22
22
— —
— —
16
16
— —
— —
24
24
14
14
22
22
16
16
24
24
— — 0
0
—
2
2
— — 0
0
—
2
2
— —
0
—
2
2
0
—
2
2
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