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Table 2-2 Instruction Set (cont)
(1) Data Transfer Instructions
Mnemonic
Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation
MOV
MOV.L @(d:16,ERs),ERd L
MOV.L @(d:24,ERs),ERd L
MOV.L @ERs+,ERd
L
MOV.L @aa:16,ERd
L
MOV.L @aa:24,ERd
L
MOV.L ERs,@ERd
L
MOV.L ERs,@(d:16,ERd) L
MOV.L ERs,@(d:24,ERd) L
MOV.L ERs,@–ERd
L
MOV.L ERs,@aa:16
L
MOV.L ERs,@aa:24
L
POP
POP.W Rn
W
POP.L ERn
L
PUSH
PUSH.W Rn
W
PUSH.L ERn
L
MOVFPE MOVFPE@aa:16,Rd
B
MOVTPE MOVTPE Rs,@aa:16
B
(2) Arithmetic Operation Instructions
Mnemonic
Size #xx Rn @ERn @(d,ERn) @ERn+/@–ERn @aa @(d,PC) @@aa — Operation
ADD
ADD.B #xx:8,Rd
B
2
ADD.B Rs,Rd
B
ADD.W #xx:16,Rd
W
4
ADD.W Rs,Rd
W
ADD.L #xx:32,ERd
L
6
ADD.L ERs,ERd
L
ADDX
ADDX #xx:8,Rd
B
2
ADDX Rs,Rd
B
Addressing Mode and Instruction Length (bytes)
6
10
4
6
8
4
6
10
4
6
8
4
4
Addressing Mode and Instruction Length (bytes)
2
2
2
2
@(d:16,ERs)→ERd32
@(d:24,ERs)→ERd32
ERs→ERd32,ERs32+4→@ERs32
@aa:16→ERd32
@aa:24→ERd32
ERs32→@ERd24
ERs32→@(d:16,ERd)
ERs32→@(d:24,ERd)
ERd32-4→ERd32,ERs32→@ERd
ERs32→@aa:16
ERs32→@aa:24
2
@SP→Rn16,SP+2→SP
4
@SP→ERn32,SP+4→SP
2
SP-2→SP,Rn16→@SP
4
SP-4→SP,ERn32→@SP
@aa:16→Rd (synchronized with
E clock)
Rs→@aa:16 (synchronized with
E clock)R
Rd8+#xx:8→Rd8
Rd8+Rs8→Rd8
Rd16+#xx:16→Rd16
Rd16+Rs16→Rd16
ERd32+#xx:32→ERd32
ERd32+ERs32→ERd32
Rd8+#xx:8+C→Rd8
Rd8+Rs8+C→Rd8
190
Condition Code
No. of States
Ad-
I
H
N Z V C
Normal vanced
— —
0
—
10
10
— —
0
—
14
14
— —
0
—
10
10
— —
0
—
10
10
— —
0
—
12
12
— —
0
—
8
8
— —
0
—
10
10
— —
0
—
14
14
— —
0
—
10
10
— —
0
—
10
10
— —
0
—
12
12
— —
0
—
6
6
— —
0
—
8
10
— —
0
—
6
6
— —
0
—
8
10
6
6
— —
0
—
6
6
— —
0
—
Condition Code
No. of States
Ad-
I
H
N Z V C
Normal vanced
—
2
2
—
2
2
— 1
4
4
— 1
2
2
— 2
6
6
— 2
2
2
—
3
2
2
—
3
2
2
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