2) Mulxu (W) - Hitachi H8/300H Series Programming Manual

2.2.39 (2) MULXU (W)

MULXU (MULtiply eXtend as Unsigned)
Operation
ERd × Rs → ERd
Assembly-Language Format
MULXU.W Rs, ERd
Operand Size
Word
Description
This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination operand) by the
contents of a 16-bit register Rs (source operand) and stores the result in the 32-bit register ERd. Rs
can be the upper part (Ed) or lower part (Rd) of ERd. The operation performed is 16-bit × 16-bit
→ 32-bit multiplication.
ERd
Don't care Multiplicand
16 bits
Available Registers
ERd: ER0 to ER7
Rs: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Register direct MULXU.W
Notes
Condition Code
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Rs
× →
Multiplier
16 bits
Operands
1st byte
Rs, ERd 5 2
131
I UI H U N
— — — — — — — —
ERd
Product
32 bits
Instruction Format
2nd byte 3rd byte
rs 0 erd
Multiply
Z V C
No. of
States
4th byte
22