1) Divxs (B) - Hitachi H8/300H Series Programming Manual

2.2.26 (1) DIVXS (B)

DIVXS (DIVide eXtend as Signed)
Operation
Rd ÷ Rs → Rd
Assembly-Language Format
DIVXS.B Rs, Rd
Operand Size
Byte
Description
This instruction divides the contents of a 16-bit register Rd (destination register) by the contents
of an 8-bit register Rs (source register) and stores the result in the 16-bit register Rd. The division
is signed. The operation performed is 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder. The
quotient is placed in the lower 8 bits of Rd. The remainder is placed in the upper 8 bits of Rd.
Rd
Dividend
16 bits
Valid results are not assured if division by zero is attempted or an overflow occurs. For
information on avoiding overflow, see DIVXS Instruction, Zero Divide, and Overflow.
Available Registers
Rd: R0 to R7, E0 to E7
Rs: R0L to R7L, R0H to R7H
Rs
→
÷ Divisor
8 bits
Condition Code
I UI H
— — — —
H: Previous value remains unchanged.
N: Set to 1 if the quotient is negative;
otherwise cleared to 0.
Z: Set to 1 if the divisor is zero; otherwise
cleared to 0.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Rd
Remainder Quotient
8 bits 8 bits
82
Divide Signed
U N Z V C
— —