2) Dec (W) - Hitachi H8/300H Series Programming Manual

2.2.25 (2) DEC (W)

DEC (DECrement)
Operation
Rd – 1 → Rd
Rd – 2 → Rd
Assembly-Language Format
DEC.W #1, Rd
DEC.W #2, Rd
Operand Size
Word
Description
This instruction subtracts the immediate value 1 or 2 from the contents of a 16-bit register Rd
(destination register) and stores the result in the 16-bit register Rd.
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Register direct DEC.W
Register direct DEC.W
Notes
An overflow is caused by the operations H'8000 – 1 → H'7FFF, H'8000 – 2 → H'7FFE, and
H'8001 – 2 → H'7FFF.
Operands
1st byte
#1, Rd 1 B
#2, Rd 1 B
80
Condition Code
I UI H U
— — — —
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
cleared to 0.
Z: Set to 1 if the result is zero; otherwise
cleared to 0.
V: Set to 1 if an overflow occurs (the
previous value in Rd was H'8000);
otherwise cleared to 0.
C: Previous value remains unchanged.
Instruction Format
2nd byte 3rd byte
5 rd
D rd
Decrement
N Z V C
—
No. of
States
4th byte
I 2
2