Hitachi H8/300H Series Programming Manual page 235

Figure 2-1 shows timing waveforms for the address bus and the RD and WR (HWR or LWR)
signals during execution of the above instruction with an 8-bit bus, using 3-state access with no
wait states.
ø
Address bus
RD
WR
(HWR or LWR)
of instruction
Figure 2-1 Address Bus, RD, and WR (HWR or LWR) Timing
R:W 2nd
Fetching Fetching
3rd byte 4th byte
of instruction
(8-bit bus, 3-state access, no wait states)
High level
Internal
operation
Fetching
1st byte of
jump address
227
R:W EA
Fetching
2nd byte of
jump address