2) And (W) - Hitachi H8/300H Series Programming Manual

2.2.4 (2) AND (W)

AND (AND logical)
Operation
Rd ∧ (EAs) → Rd
Assembly-Language Format
AND.W <EAs>, Rd
Operand Size
Word
Description
This instruction ANDs the source operand with the contents of a 16-bit register Rd (destination
register) and stores the result in the 16-bit register Rd.
Available Registers
Rd: R0 to R7, E0 to E7
Rs: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Immediate AND.W
Register direct AND.W
Notes
Operands
1st byte
#xx:16, Rd 7 9
Rs, Rd 6 6
48
Condition Code
I UI H U
— — — —
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
cleared to 0.
Z: Set to 1 if the result is zero; otherwise
cleared to 0.
V: Always cleared to 0.
C: Previous value remains unchanged.
Instruction Format
2nd byte 3rd byte
6 rd
rs rd
Logical AND
N Z V C
0 —
No. of
States
4th byte
IMM 4
2