1) Mulxu (B) - Hitachi H8/300H Series Programming Manual

2.2.39 (1) MULXU (B)

MULXU (MULtiply eXtend as Unsigned)
Operation
Rd × Rs → Rd
Assembly-Language Format
MULXU.B Rs, Rd
Operand Size
Byte
Description
This instruction multiplies the lower 8 bits of a 16-bit register Rd (destination operand) by the
contents of an 8-bit register Rs (source operand) and stores the result in the 16-bit register Rd. If
Rd is a general register, Rs can be the upper part (RdH) or lower part (RdL) of Rd. The operation
performed is 8-bit × 8-bit → 16-bit multiplication.
Rd
Don't care Multiplicand
8 bits
Available Registers
Rd: R0 to R7, E0 to E7
Rs: R0L to R7L, R0H to R7H
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Register direct MULXU.B
Notes
Rs
×
Multiplier
8 bits
Operands
1st byte
Rs, Rd 5 0
130
Condition Code
I UI H
— — — — — — — —
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Rd
→
Product
16 bits
Instruction Format
2nd byte 3rd byte
rs rd
Multiply
U N Z V C
No. of
States
4th byte
14