1) Shal (B) - Hitachi H8/300H Series Programming Manual

2.2.53 (1) SHAL (B)

SHAL (SHift Arithmetic Left)
Operation
Rd (left arithmetic shift) → Rd
Assembly-Language Format
SHAL.B Rd
Operand Size
Byte
Description
This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the left. The
most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.
MSB
C b
Available Registers
Rd: R0L to R7L, R0H to R7H
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Register direct SHAL.B
Notes
The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag.
. . . . . .
7
Operands
1st byte
Rd 1
Condition Code
I UI H
— — — —
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
cleared to 0.
Z: Set to 1 if the result is zero; otherwise
cleared to 0.
V: Set to 1 if an overflow occurs; otherwise
cleared to 0.
C: Receives the previous value in bit 7.
LSB
0
b
0
Instruction Format
2nd byte 3rd byte
0 8 rd
161
Shift Arithmetic
U N Z V C
No. of
States
4th byte
2