2) Divxu (W) - Hitachi H8/300H Series Programming Manual

2.2.27 (2) DIVXU (W)

DIVXU (DIVide eXtend as Unsigned)
Operation
ERd ÷ Rs → ERd
Assembly-Language Format
DIVXU.W Rs, ERd
Operand Size
Word
Description
This instruction divides the contents of a 32-bit register ERd (destination register) by the contents
of a 16-bit register Rs (source register) and stores the result in the 32-bit register ERd. The
division is unsigned. The operation performed is 32 bits ÷ 16 bits → 16-bit quotient and 16-bit
remainder. The quotient is placed in the lower 16 bits (Rd) of the 32-bit register ERd. The
remainder is placed in the upper 8 bits of (Ed).
ERd
Dividend
32 bits
Valid results are not assured if division by zero is attempted or an overflow occurs. For
information on avoiding overflow, see DIVXU Instruction, Zero Divide, and Overflow.
Available Registers
ERd: ER0 to ER7
Rs: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Register direct DIVXU.W
Notes
Rs
→
÷ Divisor
16 bits
Operands
1st byte
Rs, ERd 5
Condition Code
I UI H
— — — —
H: Previous value remains unchanged.
N: Set to 1 if the divisor is negative;
otherwise cleared to 0.
Z: Set to 1 if the divisor is zero; otherwise
cleared to 0.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
ERd
Remainder Quotient
16 bits 16 bits
Instruction Format
2nd byte 3rd byte
3 rs 0 ERd
91
Divide
U N Z V C
— —
No. of
States
4th byte
22