2) Shll (W) - Hitachi H8/300H Series Programming Manual

2.2.55 (2) SHLL (W)

SHLL (SHift Logical Left)
Operation
Rd (left logical shift) → Rd
Assembly-Language Format
SHLL.W Rd
Operand Size
Word
Description
This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the left. The
most significant bit shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.
MSB
C b
15
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Register direct SHLL.W
Notes
The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.
. . . . . .
Operands
1st byte
Rd 1 0
168
Condition Code
I UI H U
— — — —
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
cleared to 0.
Z: Set to 1 if the result is zero; otherwise
cleared to 0.
V: Always cleared to 0.
C: Receives the previous value in bit 15.
LSB
0
b
0
Instruction Format
2nd byte 3rd byte
1 rd
Shift Logical
N Z V C
0
No. of
States
4th byte
2