2) Shlr (W) - Hitachi H8/300H Series Programming Manual

2.2.56 (2) SHLR (W)

SHLR (SHift Logical Right)
Operation
Rd (right logical shift) → Rd
Assembly-Language Format
SHLR.W Rd
Operand Size
Word
Description
This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the right. The
least significant bit shifts into the carry flag. The most significant bit (bit 15) is cleared to 0.
MSB
0
b
15
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Register direct SHLR.W
Notes
. . . . . .
Operands
1st byte
Rd 1
171
Condition Code
I UI H
— — — —
H: Previous value remains unchanged.
N: Always cleared to 0.
Z: Set to 1 if the result is zero; otherwise
cleared to 0.
V: Always cleared to 0.
C: Receives the previous value in bit 0.
LSB
b C
0
Instruction Format
2nd byte 3rd byte
1 1 rd
Shift Logical
U N Z V C
0 0
No. of
States
4th byte
2