Hitachi H8/300H Series Programming Manual page 25

Table 1-2 Instruction Set Overview (cont)
Function Instruction #xx Rn
Branch Bcc, BSR — —
JMP, JSR — —
RTS — —
System
— —
TRAPA
control
RTE — —
SLEEP — —
LDC B B
STC — B
ANDC, B —
ORC,
XORC
NOP — —
Block data
EEPMOV.B — —
transfer
EEPMOV.W — —
Legend
B: Byte
W: Word
L: Longword
: Newly added instruction in H8/300H CPU
Notes: 1. The operand size of the ADDS and SUBS instructions of the H8/300H CPU has been changed to longword size. (In the
H8/300 CPU it was word size.)
2. Because of its larger address space, the H8/300H CPU uses a 24-bit absolute address for the JMP and JSR instructions.
(The H8/300 CPU used 16 bits.)
@ERn @(d:16,ERn) @(d:24,ERn)
— — —
—
—
— — —
— — —
— — —
— — —
W W W
W W W
— — —
— — —
— — —
— — —
Addressing Modes
@ERn+/@–ERn @aa:8 @aa:16 @aa:24 @(d:8,PC) @(d:16,PC) @@aa:8 —
— — —
— — —
— — —
— — —
— — —
— — —
W — W
W — W
— — —
— — —
— — —
— — —
17
— —
*
2
— —
— — — —
— —
— —
— — — —
— — — —
W — — —
W — — —
—
— — —
— — — —
— — — —
— — — —
—
—
—
—
—