3) Dec (L) - Hitachi H8/300H Series Programming Manual

2.2.25 (3) DEC (L)

DEC (DECrement)
Operation
ERd – 1 → ERd
ERd – 2 → ERd
Assembly-Language Format
DEC.L #1, ERd
DEC.L #2, ERd
Operand Size
Longword
Description
This instruction subtracts the immediate value 1 or 2 from the contents of a 32-bit register ERd
(destination register) and stores the result in the 32-bit register ERd.
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode*
Register direct DEC.L
Register direct DEC.L
Notes
An overflow is caused by the operations H'80000000 – 1 → H'7FFFFFFF, H'80000000 – 2 →
H'7FFFFFFE, and H'80000001 – 2 → H'7FFFFFFF.
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Previous value remains unchanged.
Operands
1st byte
#1, ERd 1 B
#2, ERd 1 B
81
I UI H U N
— — — —
cleared to 0.
cleared to 0.
cleared to 0.
Instruction Format
2nd byte 3rd byte
7 0 erd
F 0 erd
Decrement
Z V C
—
No. of
States
4th byte
2
2