Hitachi H8/300H Series Programming Manual page 37

4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn), the lower 24 bits
of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or
longword access, the register value should be even.
• Register indirect with pre-decrement—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result becomes the address of a memory
operand. The result is also stored in the address register. The value subtracted is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the
resulting register value should be even.
5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute
address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long
(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all
assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension.
A 24-bit absolute address can access the entire address space. Table 1-5 indicates the accessible
address ranges.
Table 1-5 Absolute Address Access Ranges
Normal Mode
8 bits H'FF00 to H'FFFF
(@aa:8) (65,280 to 65,535)
16 bits H'0000 to H'FFFF
(@aa:16) (0 to 65,535)
24 bits H'0000 to H'FFFF
(@aa:24) (0 to 65,535)
For further details on the accessible range, see the relevant microcontroller hardware manual.
6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16),
or 32-bit (#xx:32) immediate data as an operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the second or fourth byte of the
instruction, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in the
second byte of the instruction, specifying a vector address.
Advanced Mode
H'FFFF00 to H'FFFFF
(16,776,960 to 16,777,215)
H'000000 to H'007FFF, H'FF8000 to H'FFFFFF
(0 to 32,767, 16,744,448 to 16,777,215)
H'00000 to H'FFFFF
(0 to 16,777,215)
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