2) Extu (L) - Hitachi H8/300H Series Programming Manual

2.2.30 (2) EXTU (L)

EXTU (EXTend as Unsigned)
Operation
0 → (<bits 31 to 16> of ERd>)
Zero extend
Assembly-Language Format
EXTU.L ERd
Operand Size
Longword
Description
This instruction extends the lower 16 bits (general register Rd) in a 32-bit register ERd to
longword data by padding with zeros. That is, it clears the upper 16 bits of ERd (bits 31 to 16) to
0.
ERd
Don't care
16 bits
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Register direct EXTU.L
Notes
16 bits
Operands
1st byte
ERd 1
Condition Code
I UI H
— — — —
H: Previous value remains unchanged.
N: Always cleared to 0.
Z: Set to 1 if the result is zero; otherwise
cleared to 0.
V: Always cleared to 0.
C: Previous value remains unchanged.
ERd
Zero extension
16 bits 16 bits
Instruction Format
2nd byte 3rd byte
7 7 0 erd
101
Zero Extension
U N Z V C
0 0 —
No. of
States
4th byte
2