Andc - Hitachi H8/300H Series Programming Manual

2.2.5 ANDC

ANDC (AND Control register)
Operation
CCR ∧ #IMM → CCR
Assembly-Language Format
ANDC #xx:8, CCR
Operand Size
Byte
Description
This instruction ANDs the contents of the condition-code register (CCR) with immediate data and
stores the result in the condition-code register. No interrupt requests, including NMI, are accepted
immediately after execution of this instruction.
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Immediate ANDC
Notes
Operands
1st byte
#xx:8, CCR 0 6
50
Condition Code
I UI H U
I: Stores the corresponding bit of the result.
UI: Stores the corresponding bit of the result
H: Stores the corresponding bit of the result.
U: Stores the corresponding bit of the result
N: Stores the corresponding bit of the result.
Z: Stores the corresponding bit of the result.
V: Stores the corresponding bit of the result.
C: Stores the corresponding bit of the result.
Instruction Format
2nd byte 3rd byte
IMM
Logical AND with CCR
N Z V C
No. of
States
4th byte
2