Hitachi H8/300H Series Programming Manual page 101

DIVXU
DIVXU (DIVide eXtend as Unsigned)
Example 2: Zero-extend divisor from 8 to 16 bits and dividend from 16 to 32 bits before dividing
EXTU.W R0
BEQ ZERODIV
EXTU.L ER1
EXTU.W R0, ER1
RTS
ZERODIV:
Instead of 16 bits ÷ 8 bits, the operation performed is 32 bits ÷ 16 bits → quotient (16 bits) and
remainder (16 bits), and no overflow occurs. The 16-bit quotient is stored in R1 and the 8-bit
remainder in the lower 8 bits of E1. The upper 8 bits of E1 are all 0.
ER1
Sign extension
ER1
Remainder
; Zero-extend 8-bit divisor to 16 bits
; Branch to ZERODIV if R0 = 0
; Zero-extend 16-bit dividend to 32 bits
; Divide using DIVXU.W
; Zero-divide handling routine
R0L
Divisor
R1
Dividend
R0L
Sign extension
Dividend
Quotient
93
Divisor
Divide