3) Shar (L) - Hitachi H8/300H Series Programming Manual

2.2.54 (3) SHAR (L)

SHAR (SHift Arithmetic Right)
Operation
ERd (right arithmetic shift) → ERd
Assembly-Language Format
SHAR.L ERd
Operand Size
Longword
Description
This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the right.
Bit 0 shifts into the carry flag. Bit 31 shifts into itself. Since bit 31 remains unaltered, the sign
does not change.
MSB
b
31
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Register direct SHAR.L
Notes
. . . . . .
Operands
1st byte
ERd 1
Condition Code
I UI H
— — — —
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
cleared to 0.
Z: Set to 1 if the result is zero; otherwise
cleared to 0.
V: Set to 1 if an overflow occurs; otherwise
cleared to 0.
C: Receives the previous value in bit 0.
LSB
b C
0
Instruction Format
2nd byte 3rd byte
1 B 0 erd
166
Shift Arithmetic
U N Z V C
0
No. of
States
4th byte
2