Hitachi H8/300H Series Programming Manual page 100

DIVXU
DIVXU (DIVide eXtend as Unsigned)
DIVXU Instruction, Zero Divide, and Overflow
Zero divide and overflow are not detected in the DIVXU instruction. A program like the following
can detect zero divisors and avoid overflow.
1. Programming solutions for DIVXU.B R0L, R1
Example 1: Divide upper 8 bits and lower 8 bits of 16-bit dividend separately and obtain 16-bit
quotient
CMP.B #0, R0L
BEQ ZERODIV
MOV.B R1H,R2L
EXTU.W R2
DIVXU.B R0L, R2
MOV.B R2H, R1H
DIVXU.B R0L, R1
MOV.B R2L, R2H
MOV.B R1L, R2L
RTS
ZERODIV:
The resulting operation is 16 bits ÷ 8 bits → quotient (16 bits) and remainder (8 bits), and no
overflow occurs. The 16-bit quotient is stored in R2, the 8-bit remainder in R1H.
R0L
R1
Dividend
R2
Sign extension
R2
Remainder (part) Quotient (high)
R1
Remainder (part)
R1
Remainder
R1
Remainder
R2
Quotient
; R0L = 0? (Zero divisor?)
; Branch to ZERODIV if R0L = 0
; Copy upper 8 bits of dividend to R2L and
; zero-extend to 16 bits
(*1).
; Divide upper 8 bits of dividend
(*2)
; R2H → R1H (store partial remainder in R1H)
(*3)
; Divide lower 8 bits of dividend (including repeated division of
(*4)
upper 8 bits)
; Store upper part of quotient in R2H
; Store lower part of quotient in R2L
(*5)
; Zero-divide handling routine
Divisor
( 1) *
Dividend (high)
( 2)
*
( 3)
Dividend (low) *
( 4)
Quotient (low) *
Quotient (low)
( 5)
*
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Divide