Mixing Processors; Supported Power-Up Voltage Sequence - Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet

For reliable operation, always terminate unused inputs or bi-directional signals to their
respective deasserted states. A resistor must be used when tying bi-directional signals
to power or ground, also allowing for system testability. Unused pins of Intel
QuickPath Interconnect and FB-DIMM ports may be left as no-connects since
termination is provided on the processor silicon.
Unused outputs may be terminated on the system board or left connected. Note that
leaving unused outputs unterminated may interfere with some Test Access Port (TAP)
functions, complicate debug probing, and prevent boundary scan testing. Signal
termination for these signal types is discussed in latest revisions of Intel
Processor 9300 Series and Intel
Guide.
Debug pins have ODT and can be left as no-connects. Their routing guidelines are
provided in the Intel
9500 Series Platform Design Guide.
2.10

Mixing Processors

Intel will support mixing CPUs in the same system or hard partition as defined below. A
hard partition is a smaller system capable of booting an OS, consisting of one or more
processors, memory and I/O controller hubs that are formed by domain partitioning.
1. CPUs from adjacent steppings. For example if one cpu is from stepping N, and
another cpu is from the next stepping, N+1, then CPU
Similarly CPU
2. All CPUs in the system or hard partition must have the same core clock speed or
speed range and the same cache size.
3. All Intel
are disabled or in slow mode.
Additionally, for the Intel
4. If variable frequency mode (VFM) is enabled in one CPU it must be enabled in all
CPUs. If VFM mode is disabled in one CPU it must be disabled in all CPUs.
5. Mixing an enabled VFM part with an fixed frequency mode (FFM) part within the
same system or hard partition.
2.11

Supported Power-up Voltage Sequence

The supported order of voltage sequencing for the processor, detailed in
and Figure 2-18
VCCUNCORE and VCCCORE for the Intel
and followed by VCCCACHE for the Intel
customers need to apply VccArarat(12V) before VCC33_SM, the processor will not
sustain damage. The application of VCC33_SM before VccArarat(12V) allows the PIROM
to be read before the processor is powered.
Once started, the power up sequence must complete within 1000 ms, as defined by the
time limit for PWRGOOD to be asserted. VCC33_SM is brought up first to allow
platforms to read the socket Processor Information data and the PROCTYPE pin.
VccArarat (12V) is the input voltage to the Ararat regulator. The VCCA supply is used to
power the processor's analog circuits. VCCIO is used to power the I/O circuits. Once
VCCIO is up and stable the external environment can generate the SYSINT clock
signals. Once the SYSINT clocks are valid, the external environment can assert the
64
®
Itanium
® ®
Itanium Processor 9300 Series and Intel
is not compatible with CPU
N
® QPI links must have the same data rate, except for Intel
®
Itanium
and Table 2-39, is VCC33_SM, VccArarat(12V), VCCA, VCCIO,
®
Processor 9500 Series Platform Design
N
.
N+2
®
Processor 9300 Series:
® ®
Itanium Processor 9500 Series processor
® ®
Itanium Processor 9300 Series processor. If
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
®
®
Itanium
® ®
Itanium Processor
and CPU are compatible.
N+1
® QPI links which
Figure 2-17
®